1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of controlling the etching of a layer of silicon nitride relative to a layer of silicon dioxide.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Etching processes, both wet and dry processes, are commonly employed to selectively etch one material relative to another material. Certain materials exhibit a relatively high etch selectivity relative to another material when both materials are exposed to the same etching process. For example, silicon nitride and silicon dioxide are two very common materials that may be selectively etched relative to one another using the appropriate etch chemistries, wherein the silicon nitride is removed and the silicon dioxide is only slightly etched. For example, silicon nitride may be selectively etched relative to silicon dioxide by performing a wet etching process using hot phosphoric acid as the etchant.
There are many applications where silicon nitride is etched relative to an underlying layer of silicon dioxide. In some of those applications, it is very important that the etching process consume all of the silicon nitride while not consuming too much or too little of the underlying layer of silicon dioxide. One situation where silicon nitride is etched relative to silicon dioxide is in the process used to form isolations structures for a semiconductor device. To make an integrated circuit on a semiconducting substrate, the various semiconductor devices, e.g., transistors, capacitors, etc., are electrically isolated from one another by so-called isolation structures. Currently, most sophisticated integrated circuit devices employ so-called shallow trench isolation (STI) structures. As the name implies, STI structures are made by forming a relatively shallow trench in the substrate and thereafter filling the trench with an insulating material, such as silicon dioxide. One technique used to form STI structures initially involves growing a pad oxide layer on the substrate and depositing a pad nitride layer on the pad oxide layer. Thereafter, using traditional photolithography and etching processes, the pad oxide layer and the pad nitride layers are patterned by performing an etching process through a patterned photoresist mask. Then, an etching process is performed to form trenches in the substrate for the STI structure using the patterned pad oxide layer and pad nitride layer as an etch mask. Thereafter, a deposition process is performed to overfill the trenches with an insulating material, such as silicon dioxide. A chemical mechanical polishing (CMP) process is then performed using the pad nitride layer as a polish-stop layer to remove the excess insulation material. Then, a subsequent deglazing (etching) process may be performed to insure that the insulating material is removed from the surface of the pad nitride layer. This deglaze process removes some of the STI structures. Thereafter, an etching process is performed to remove the pad nitride layer relative to the pad oxide layer. After the pad nitride layer is removed, the pad oxide layer may be used in subsequent processing operations, such as to act as a screen oxide during various ion implantation processes that are performed to form various doped regions in the semiconducting substrate. In many applications, it is very important that the thickness of the pad oxide layer be within a very tight thickness range.
The formation and removal of sidewall spacers is another situation where silicon nitride is commonly etched relative to an underlying layer of silicon dioxide. Typically, a relatively thin silicon dioxide liner layer is formed on the sidewalls of a gate electrode structure of a transistor and a silicon nitride sidewall spacer is formed on the silicon dioxide liner layer. In some process flows, it is desirable to remove the silicon nitride sidewall spacer while leaving the silicon dioxide liner layer in place. In such applications, it is very important to insure that all of the silicon nitride sidewall spacer is removed, while at the same time not excessively consuming the relatively thin silicon dioxide liner layer.
When silicon nitride is etched relative to silicon dioxide in a hot phosphoric acid bath, the amount of silicon dissolved in the bath increases due to the consumption of the silicon nitride material. This is generally referred to as “silicon loading” of the etching bath. If the silicon loading becomes too high, the etch rate of silicon dioxide greatly decreases and may even approach zero. In applications where a slight etching of an underlying layer of silicon dioxide is desired to insure complete removal of an overlying layer of silicon nitride, a relatively high silicon loading may effectively prevent or at least reduce the likelihood that the silicon nitride material is completely removed. High silicon loading of the etch bath can also lead to increased particle contamination of the processed wafers, which may adversely impact product yields.
Prior art techniques that have been employed in attempting to control the silicon loading of an etch bath when etching silicon nitride relative to silicon dioxide have been, at best, marginally successful and they have frequently not been applied in any uniform manner. One technique involves drawing off a certain amount of the existing etchant chemicals from the bath and adding a corresponding amount of “new” etchant chemicals after a set period of time has elapsed or after a set number of lots have been processed. For example, every three or so days, measurements will be taken of wafers processed in the etch bath to determine the etch rate of silicon dioxide in the bath. In some cases, using this technique, it has been determined that the etch rate of silicon dioxide may vary quite a bit, e.g., ±100%, between measurement periods. Once it is determined that the etch rate of silicon dioxide is too low, a predetermined amount of the existing etchant bath will be drained off and replaced with a corresponding amount of the “new” etchant chemicals—a “drain/replenish” operation will be performed. If it is determined that the etch rate of silicon dioxide is too high, the etch bath is seasoned with dummy silicon nitride wafers to increase the silicon loading and bring the etch rate back to a desired target level. This process is performed on an arbitrary schedule, e.g., every three days, independent of the number of wafers processed in the bath during that period. If the etch rate of the silicon dioxide layer was determined to be acceptable, the drain/replenish cycle was continued. If the etch rate of the silicon dioxide layer was determined to be unacceptable, the drain/replenish cycle was modified and additional testing on processed wafers was performed until such time as there was a relatively high degree of confidence that the etching process was producing acceptable results. This relatively crude form of process control resulted in an etching process that was less stable than would otherwise be desired and lead to defective devices and additional reworking of some defective substrates.
The present disclosure is directed to various methods of controlling the etching of silicon nitride relative to silicon dioxide that may solve or at least reduce one or more of the problems identified above.